{"id":106,"date":"2018-04-30T09:04:14","date_gmt":"2018-04-30T09:04:14","guid":{"rendered":"http:\/\/asral.unimap.edu.my\/?page_id=106"},"modified":"2021-07-14T00:10:14","modified_gmt":"2021-07-14T00:10:14","slug":"teaching","status":"publish","type":"page","link":"http:\/\/asral.unimap.edu.my\/?page_id=106","title":{"rendered":"Teaching"},"content":{"rendered":"\n<p><strong>System On Chip Design<\/strong><br> Course Content Summary:<br> &#8211; Design methodology<br> &#8211; IP design for reuse<br> &#8211; Platform based design<br> &#8211; Essential system on chip components: processors, memory, system-level interconnect<br> &#8211; Hardware\/software co-design<br> &#8211; Behavioral synthesis<br> &#8211; Physical design for SOC<br> &#8211; Energy management for SOC<br> &#8211; Multiprocessor system on chip<br> &#8211; Application study: Multimedia SOC<br> &#8211; Latest trend &amp; practical consideration in SOC design<\/p>\n\n\n\n<p><strong>VLSI Design<\/strong><br> Course content summary:<br>&#8211; Review of Transistor Level Design<br>      &#8211; CMOS transistor characteristics, Fabrication, CMOS circuit level design<br>&#8211; Circuit Characterization and Performance Estimation<br>      &#8211; Speed: delay model and timing analysis<br>       &#8211; Power: source of power consumption<br>       &#8211; Wires: Interconnect modeling<br>       &#8211; Circuit characterization<br>&#8211; High Level Design Methodology<br>       &#8211; VLSI design approach<br>       &#8211; VLSI design flows: Logic design and synthesis<br>       &#8211; VLSI design flows: Automated place and route<br>&#8211; Advance VLSI Design<br>      &#8211; High-speed design<br>      &#8211; Low power architecture<br>&#8211; Design Strategies for Test<br>      &#8211; Design for manufacturability<br>      &#8211; Test pattern generation<\/p>\n\n\n\n<p><strong>Computer Organization and Architecture<\/strong><br> Course content summary:<br> &#8211; Introduction to Computer Architecture<br> &#8211; Computer function and Interconnection<br> &#8211; Cache Memory<br> &#8211; Internal Memory<br> &#8211; External Memory<br> &#8211; Input and Output<br> &#8211; Operating System<br> &#8211; Instruction Sets: Characteristics and Functions<br> &#8211; Instruction sets: Addressing Modes and Formats<br> &#8211; Processor Structure and Function<br> &#8211; RISC: Reduced Instruction Set Computers<br> &#8211; Instruction-Level Parallelism and Superscalar Processor<br> &#8211; Control Unit Operation<br> &#8211; Microprogrammed Control<\/p>\n\n\n\n<p><strong>Microcontroller<\/strong><br> Course Content Summary:<br> &#8211; Introduction to Embedded System<br> &#8211; Microcontroller<br> &#8211; Assembly language programming and<br> &#8211; C programming<br> &#8211; I\/O ports<br> &#8211; Timer &amp; Counter<br> &#8211; Serial Communications<br> &#8211; Interrupts<br> &#8211; Design Consideration<br> &#8211; Multiprocessor<br> &#8211; Real-Time I\/O and Multitasking<br> &#8211; Hardware interfacing and timing<\/p>\n\n\n\n<p><strong>Analog Integrated Circuit Design<\/strong><br> Course Content Summary:<br> &#8211; MOS Transistor<br> &#8211; Second Order Effects<br> &#8211; Basic Analog Cells<br> &#8211; Single Stage Amplifier<br> &#8211; Differential Amplifier<br> &#8211; MOS Operational Amplifier (Op-Amp)<br> &#8211; Op-Amp Application<\/p>\n","protected":false},"excerpt":{"rendered":"<p>System On Chip Design Course Content Summary: &#8211; Design methodology &#8211; IP design for reuse &#8211; Platform based design &#8211; Essential system on chip components: [&#8230;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages\/106"}],"collection":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=106"}],"version-history":[{"count":6,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages\/106\/revisions"}],"predecessor-version":[{"id":433,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages\/106\/revisions\/433"}],"wp:attachment":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=106"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}