The Faculty of Electronic Engineering Technology, UniMAP, is well equipped with various laboratory and research facilities for microelectronics. For VLSI circuit and system design, it has complete CAD tools and FPGA for designing from system concepts down to VLSI layout verification.<\/p>\n\n\n\n
Detail software and hardware available:<\/p>\n\n\n\n
Synopsys Digital Front-End Design<\/strong> Synopsys Digital Back-End Design<\/strong> Intel FPGA:<\/strong> Xilinx FPGA:<\/strong> The Faculty of Electronic Engineering Technology, UniMAP, is well equipped with various laboratory and research facilities for microelectronics. For VLSI circuit and system design, it […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages\/101"}],"collection":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=101"}],"version-history":[{"count":7,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages\/101\/revisions"}],"predecessor-version":[{"id":439,"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=\/wp\/v2\/pages\/101\/revisions\/439"}],"wp:attachment":[{"href":"http:\/\/asral.unimap.edu.my\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=101"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\u2022 HDL Verification – VCS MX
\u2022 Logic Synthesis – Design Compiler
\u2022 Static Timing Analysis (STA) – PrimeTime
\u2022 Formal Verification – Formality
\u2022 IP – DesignWare Library
\u2022 ATPG – TetraMax<\/p>\n\n\n\n
\u2022 Physical Implementation – IC Compiler (Automatic Place and Route)
\u2022 Physical Verification – ICV
\u2022 Parasitic Extraction \u2013 StarRC
\u2022 Spice Simulation – HSPICE<\/p>\n\n\n\n
\u2022 DE1-SoC
\u2022 DE2-70 Development Board
\u2022 DE10-Nano
\u2022 DE10-Lite
\u2022 Cyclone III Video Development Board<\/p>\n\n\n\n
\u2022 Xilinx Zynx All Programmable SOC Developmen Board
\u2022 Xilinx Nexys 4 DDR<\/p>\n","protected":false},"excerpt":{"rendered":"